Thus, this paper provides a threshold to build more complex arithmetic systems using reversible logic, thus increasing the performance of computing systems with low power dissipation. There is a power reduction of about 64.41% and 14.06% at 180nm and 90nm CMOS process technologies respectively in reversible BUS gate as compared to conventional CMOS-based designs. Manchester adder and C17 circuit of ISCAS'85 (International Symposium on Circuits and Systems-1985) benchmark suite using BUS gate are designed and verified using Electronic Design Automation (EDA) tools. The proposed BUS gate is implemented on Field Programmable Gate Array (FPGA) and simulated using 180nm and 90nm CMOS process technologies. In this paper, a new reversible Basic, Universal and Special (BUS) gate is proposed that is available as a single gate with multiple functionalities as basic (AND, OR & NOT), universal (NAND & NOR) and special gate (EXOR). Basic and universal gates are the basic building blocks of digital system. Optimization of device power can be achieved using reversible logic computation and this technique can be applied to a variety of low power applications such as optical computing, nanotechnology, Complementary Metal Oxide Semiconductor (CMOS) Very Large-Scale Integrated Circuits (VLSI) design and many more.
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